1. Field of the Invention
The present invention relates in general to apparatus for providing clock signals in a computer and in particular to an apparatus for dynamically switching between multiple clock sources.
2. Description of the Prior Art
High and low frequency clock sources are used in computer systems to take full advantage of the high speed operation of current microprocessors, on-board memories and the like and the low speed operation of off-board memories and other peripheral devices such as input/output devices.
The switching circuits used for switching between high and low frequency clock sources are either synchronous or asynchronous and heretofore both have been found to have certain disadvantages. For example, a disadvantage of prior known asynchronous clock switching circuits is that the circuits usually introduce "glitches", i.e. unwanted spikes, in the clock output or unwanted losses of clock pulses when the circuit switches between high and low frequency clock sources. Such effects create instability in the computer or violate microprocessor (CPU) specifications. On the other hand, the use of synchronous switching circuits requires the switching to be synchronized to an external clock source. In practice, that results in the switching time taking longer to complete, requires additional overhad and prevents expedient use of dynamic switching, i.e. switching from machine cycle to machine cycle.
In order to achieve compatibility in terms of software and hardware timing, several approaches have been used in the past.
In one approach, clock switching has been limited to switching between clock sources wherein the frequency of the high clock is twice the frequency of the low clock, e.g. 16 mHz/8 mHz, 12 mHz/6 mHz or 10 mHz/5 mHz. In this way, the circuit design of the state machine is simplified, but the performance is poor, especially in the low speed mode.
In another approach relatively complicated state machines have been used to accommodate both high and low speeds but unwanted wait states are typically required. For example, in the IBM AT design using 16 mHz/8 mHz, two state machines are used. In a memory cycle involving a given memory, for instance, the 8 mHz mode will generate 1 wait state while the 16 mHz mode will generate 4 wait states.
In a computer system which uses a high clock frequency which is not twice the low clock frequency, compatibility is even more difficult to achieve. For example, in a computer system using 12 mHz and 8 mHz clock sources, the 12 mHz mode will require 2.5 wait states to maintain compatibility with the 8 mHz clock. Since fractional wait states are not possible, conventional state machines in such systems cannot provide exact compatibility. Moreover, a different design for the state machines would be required in such systems for each different set of multiple clock sources, e.g. 20 mHz/8 mHz, 16 mHz/8 mHz or 12 mHz/8 mHz, if performance is not to be sacrificed.